1	Digital Radio Example: FM modulation and demodulation in an FPGA IEEE-Denver Signal Processing Society February 19, 2009 David Farrell Dane Sprister Matthew Taylor Colorado Electronic Product Design, Inc.
2	Topics Introduction Abstract System Block Diagram Up/Down Conversion Modulation Demodulation Demonstration System Questions
3	Introduction Colorado Electronic Product Design is an engineering consulting company in Boulder, founded in 1996. Services we provide include: DSP Embedded Systems Hardware and Software Data Acquisition Telemetry Systems Motor Control Systems Programmable Logic: FPGA / CPLD / EPLD Analog Circuit Design Switching Power Supply Design PCB Design and Layout Analysis and Documentation
4	Abstract This presentation by Colorado Electronic Product Design explores an FPGA based configurable digital radio, and demonstrates an FM transceiver design. The trend in software radios is moving toward an all-digital design within a single chip. Most elements of a digital radio can now be implemented within an FPGA. A high-speed analog to digital converter board and an FPGA board are used to implement a working radio using VHDL.
5	Hardware Transceiver Implementation
6	The platform is fairly flexible The impedance of the PCB signal paths are wideband and 50 ohm Mixers, which can be bypassed, are provided for up/down conversion Key components are socket-ed, different bands can be targeted by changing out filters, etc. The ADC and DAC support over 200 MSPS The main signal processing algorithms are performed by a configurable FPGA
7	Up/Down Conversion Some Trigonometry A real mixer produces sum and difference tones or spectra: sin( ω_Ct ) • sin( ω_LO t ) = ½ cos( (ω_C- ω_LO)t ) - ½ cos( (ω_C+ ω_LO)t ) Filtering is required to select only the desired component. A complex or quadrature mixer produces a single tone or spectra: e^j ^ω^c^t• e^-j ^ω^LO^t= e^j ^(ω^c^{- ω}^LO^)t or [ cos( ω_Ct ) + j sin( ω_Ct ) ] • [cos( ω_Ct ) - j sin( ω_Ct )] = cos( (ω_C- ω_LO)t ) + j sin( (ω_C- ω_LO)t ) The mixercomplexity is doubled, real and imaginary or in phase and quadrature paths are required.
8	Quadrature Detection Trigonometry Ф is the desired time varying signal sin( ω_Ct + Ф ) • cos( ω_C t ) = ½ sin(Ф) + ½ cos( ω_Ct + Ф) Filter out the carrier and the signal remains ½ Ф ≈ ½ sin(Ф), for Ф < π/4
9	Real Down Conversion – Moving the carrier to the IF The mixed signal contains two frequencies: ω_C - ω_LO and ω_C + ω_LO If the local oscillator frequency is chosen to be ω_C – ω_IF, the two resultant frequencies are: ω_IF and 2 ω_C - ω_IF
10	Real Up Conversion – Moving the IF to the Carrier frequency The mixed signal contains two frequencies: ω_LO - ω_IF and ω_LO + ω_IF If the local oscillator frequency is chosen to be ω_C - ω_IF, the two resultant frequencies are: ω_C and ω_C - 2ω_IF
11	Bandpass Sampling Undersampling is a method that uses a sampling frequency below the Nyquist rate for the signal of interest It intentionally aliases an image of the signal into the digitized spectrum Works if the Bandwidth of the desired signal is less than ½ the sample frequency
12	FM Modulation
13	Purpose The purpose of this section is to: Present algorithms for implementation of an FPGA controlled FM modulator. Present a hardware platform that can be used to implement the design of different modulation implementations.
14	Outline of this section Overview of FM Radio and FM Radio sub carriers Outline of Direct Digital Synthesis Architecture Implementation of Modulator Reference design Overview of the Analog Board
15	Overview of FM Modulation Commercial FM radio broadcasts at 88MHz to 108MHz There is a separation of 200kHz between adjacent stations. The peak frequency deviation is 75kHz. The left and right channels are added and subtracted to generate L+R and L-R. The L+R (monophonic) and L-R (stereo) signals are preemphasized. The L-R signal is modulated and added to the L+R and 19kHz pilot signal prior to the FM modulator block.
16	Implementing FM Modulator in VHDL Signal to be transmitted is a monophonic signal. Left and right channels are not present, so they do not need to be added and subtracted to get L+R and L-R. Because left and right channels are not both present a 19kHz pilot is not required. Preemphasis is not used. The input audio signal is not DSB-SC for a 38KHz carrier (because there is no pilot signal).
17	DDS Architecture The FM reference design uses DDS architecture to modulate the line in signal.
18	Overview of DDS Architecture The phase accumulator: Tracks the phase of the sine wave. Uses a modulus n counter to allow the sine wave frequency to change quickly using a tuning word. Is incremented every system clock cycle by the value of the tuning word.
19	Overview of DDS Architecture The output of the phase accumulator is connected to a phase to amplitude converter. The value of the phase accumulator is truncated and mapped to a sine wave lookup table. Without phase accumulator truncation, the amount of memory required for the lookup table is too large.
20	VHDL Implementation Several components were used to implement the modulator: PCM3500 – audio CODEC component to read ADC values from the line in port. FM Modulator – Modulator component contains the phase accumulator and converters to calculate amplitude to frequency and frequency to tuning word. Sine Wave Look up Table. Dac5674 – output sine wave to Digital to Analog Converter
21	PCM3500 This component interfaces with the PCM3500 16-bit audio CODEC. This component shifts the 16-bit ADC value from the audio CODEC serially and stores the value in a 16-bit register.
22	FM Modulator The audio CODEC value is converted from 2’s compliment to a binary offset value. The value is then converted from an amplitude to a frequency. The frequency is converted to a tuning word value. The values used for conversions are Q16, so the values are converted back to Q0 values by shifting the values. The tuning word is added to a pre-calculated tuning word for 10.625MHz. The tuning word is added to the value in the phase accumulator (this tuning word is added to the phase accumulator every system clock cycle). The phase accumulator value is output to the top.vhd level.
23	FM Modulator Block Diagram
24	Sine Wave Look-up Table The phase accumulator value is truncated and the top 14 bits are taken into the sine wave lookup table component as an address. 16,384 amplitude points making up a full cycle of a sine wave are stored in this component as an integer array (8-bit values). The 8-bit amplitude value is output to the top.vhd level for output to the Digital to Analog Converter.
25	dac5674 The 8-bit amplitude value from the sine wave lookup table is placed in an output register in the top.vhd level (placed in the top 8-bits of the 14-bit DAC output register). The output register is mapped to the dac5674 component. The 14-bit output register is clocked out to the DAC and, if the Transmit/Receive switch is depressed, transmitted.
26	Block Diagram
27	Analog Up-Converter
28	Digital FM Demodulator Through Quadrature Detection
29	Analog Down Converter
30	FPGA Demodulation Block Diagram
31	Sampling Implementation The ADC samples a 10.7MHz IF at 66.5Mhz with 13bits resolution Significantly faster than IF of 10.7MHz provided by the analog down converter. ADC provides a Data Ready signal for latching the data bus. ADC data is in binary offset. Binary offset is converted to 2’s complement. This is done by inverting the most significant bit of the ADC data register.
32	Limiter Implementation A limiter is used to improve signal to noise ratio. The limiter hysteresis band is set to +-120 ADC counts. This squelches the ADC input noise. Similar to a comparator design in the analog domain. Output level is set to 50% of full scale to prevent overflow. When sampling a FM signal there is no information in the amplitude. Perform sign extension from 13bits to 16bits.
33	Down Sample The 66.5MHz sample frequency is then down sampled to create a 8.3125MHz IF. Latch every 8^th sample The IF frequency of 10.7 MHz is sampled at 8.3125 MHz, producing a flipped image at 5.925 MHz and a positive image at 2.3875 MHz. A center frequency of 2.3875Mhz will be chosen for the band pass filter, removing the 5.925Mhz reflection.
34	FM Demodulator Stages
35	FM Quadrature Demodulator
36	2^nd Order FIR used for the p / 2 phase shift (Hilbert Transform)
37	Hilbert Transform Response
38	2^nd Order IIR Biquad used for the Bandpass Filter
39	Bandpass Filter Response
40	Discrete time form of the Demodulator
41	Lowpass Filter Response
42	Suggested Reading
43	Suggested Reading Continued
44	Demonstration System A VHF FM Transceiver Utilizes a conventional mixer front end with an IF of 10.7MHz A high speed ADC samples the IF at 66.5MHz. A modular FPGA board decimates the signal and performs the modulation and demodulation.
45	Demonstration System
46	Beginning of Extra Supplemental Slides (the following were excluded from the talk)
47	FM Modulation – Pre-emphasis Preemphasizing the transmitted signal can reduce noise greatly. Noise increases linearly with frequency. Weaker high frequency components (beyond 2.1kHz) are boosted before the modulator using a preemphasis filter with a transfer function of H_p(jω). The higher frequency components are deemphasized in the receiver using a deemphasis filter with a transfer function of 1/H_p(jω).
48	FM Modulation and Radio Data Systems (RDS) RDS uses a 57kHz subcarrier (3^rd harmonic of 19kHz pilot). Transmits data at 1187.5 bits per second with error correction.
49	FM Modulation and Hybrid Digital Radio (HD) HD Radio combines analog and digital signals into an AM or FM radio station’s bandwidth. HD Radio provides nearly CD quality audio (CD quality is available with 100kbps transmission). There are 4 FM hybrid digital/analog modes offered: 100, 112, 125, and 150kbps. A pure digital option with up to 300kbps enabling extra features. In regular hybrid mode a station uses full 130kHz analog bandwidth and an extra 70kHz for the digital signals (using 400kHz total). Uses Coded Orthogonal Frequency Division Multiplexing (COFDM)
50	Overview of DDS Architecture A simple sine wave oscillator can be created using a reference clock, counter, and sine wave look up table. This implementation is not flexible for generating different frequencies as to generate other frequencies requires changes to the reference clock. Modulation based on divide counters are difficult to implement as division is required to move between time and frequency.
51	Performance of FM Modulator
52	What is meant by “portable VHDL” The code is not vendor specific IP cores are not used All of the source code is visible to the designer -- Example: The Hilbert Transform w0_1 <= x; B0W0_1 <= b0_1 * w0_1; B2W2_1 <= b2_1 * w2_1; rightsum1 <= B0W0_1 + B2W2_1; PROCESS (reset, demodClk) BEGIN IF (reset = '1') THEN w1_1 <= (others => '0'); -- clear taps w2_1 <= (others => '0'); y_1 <= (others => '0'); ELSIF (demodClk'EVENT and demodClk = '1') THEN w2_1 <= w1_1; -- update taps w1_1 <= w0_1; y_1 <= rightsum1(31 DOWNTO 16); -- right shift for Q16 END IF; END PROCESS;
53	Digital Radio Sensitivity
54	Fixed-point Representation
55	FPGA Implementation of the Demodulator